As transistors are formed with smaller lithographies, such as lithographies less than 100 nanometers (“nm”), variation among transistors becomes more problematic with respect to performance. More particularly, as devices are formed smaller, the susceptibility to differences in topology of such devices generally has more of an effect on performance than for example devices formed with lithographies greater than 100 nm. Along those lines, transistors formed with different lengths of diffusion (“LODs”) or pitches may have different performance levels due to such differences. By LOD, it is generally meant the distance from an edge of an active transistor gate to an edge of a neighboring shallow trench isolation (“STI”) structure. These different performance levels may exist for transistors of different LODs or pitches even though channel width and length of such transistors is the same. Furthermore, it should be understood that such transistors may have different performance even though materials for forming such transistors is the same. Another factor that exacerbates this performance difference in PMOS is a conventional stress engineering practice for lithographies of less than 100 nm technologies of having an embedded silicon germanium (“eSiGe”) layer. Growing eSiGe in PMOS source/drain regions is to increase the compressive stress along a PMOS transistor channel direction (or longitudinal x-axis direction). Some device studies have shown substantially enhanced carrier mobility for PMOS due to compressive stress along a longitudinal or x-axis direction, and tensile stress along a lateral or y-axis direction and along a vertical or z-axis direction. Therefore such eSiGe layer is conventionally used for PMOS source and drain regions for the purpose of adding stress along the channel, where such source and drain regions are uniformly etched to a same depth.
The above-mentioned LOD effect may result in significant variation among transistors. Such variations may be in one or more of the following parameters: threshold voltage (Vt), channel saturation current (Idsat), and off current (Ioff). Comparing PMOS transistors with same channel width and length (“W/L”) where some have wide LODs compared to others with narrow LODs, those PMOS transistors with a narrow LOD show degradation of Idsat due to worse mobility. In other words, when compared at a fixed Idsat, PMOS transistors with relatively narrow LODs tend to show lower Vt versus those transistors with significantly wider LODs.
These transistor performance variations could have several negative impacts upon ICs. First, such variations could introduce reduction in IC performance as lowered Idsat may result in a slower slowest path which may limit overall IC performance. Secondly, such transistor performance variations could contribute to higher Icc leakage current, because faster transistors may have higher off or standby current, and if the variation goes to a minimized state all of the Icc current could be reduced due to a tighter Ioff current distribution. Another factor is performance mismatch of transistors with same W/L due to LOD effects, and such differences may negatively affect circuit functionality in some instances.
Accordingly, it would be both desirable and useful to provide means for reducing the above mentioned variations among transistors of different LODs.